MOSFET

Note to Professors and Students: Discussion given in the following, using three applet programs, on the metal-oxide-semiconductor (MOS) field effect transistor (FET) is meant to supplement the traditional course materials of text books and lectures. It is not intended to replace them.  As such, this resource is best when used as part of lecture presentation, recitation, or homework assignments.

In this exercise we use three applets to provide a visual simulation of the MOSFET physics.  This text is an initial draft.

1. MOS Electrostatics

If a bias voltage is applied to the Gate metal, relative to the silicon substrate, which is in excess of the Threshold Voltage Vt, then charge carriers are gethered in sufficient concentration under the Gate oxide. For an n-channel MOS structure, prepared on p-type silicon, a Gate bias greater than the Threshold Voltage Vt will create an inversion n-channel under the gate oxide.

For Vt = 1.0 Volts, a Gate bias Vg > 1.0 V will induce an n-channel. In the following applet, use the arrows next to "Vg" to change the gate bias and observe when the n-channel is formed. You may change the threshold voltage and see the effect on the necessary Gate bias voltage to induce an n-channel.

A p-channel MOS structure needs a bias voltage opposite to the n-channel MOS. Change the channel-type to p-channel in the above applet. For Vt = -1 V, a gate bias Vg < -1 V shall induce a p-channel under the Gate. That is, a Gate bias which is more negative than the Threshold Voltage will induce a sufficient concentration of positive charge carriers in the channel region (inversion p-channel). Quatitatively, an inversion channel is formed if the charge carrier concentration under the Gate is greater than or equal to the carrier concentration in the bulk.

A normally-off (or enhancement-mode) n-MOSFET has a positive Vt. At Vg = 0 V, the Vg is less positive than Vt and thus no inversion n-channel is present. Likewise, a normally-off p-MOSFET has a negative Vt. The exact value of Vt is important as it controls at what applied voltage the device is switched. Its value should be well within the available battery source on the circuit.

The Threshold voltage of a MOS structure depends on the physical properties of the MOS structure such as the kind of Gate metal, oxide thickness, and silicon doping level. It also depends on any fixed charge that may be present between the Gate metal and the oxide. The complete theory is rather complicated and is a topic in other applet pages.

This very simple applet is given here to acquaint you with the channel formation in MOS structure by an applied Gate bias.

2. A MOSFET in Saturation or as a Triode.

Charge carriers in MOSFET originate in Source and flow into Drain. The total amount of charge that flows depends on how much charge is injected into channel from Source. This is controlled by the Gate-Source bias, Vgs.  The drain current may or may not depend on the voltage drop between Source and Drain. The following applet shows a visual simulation of the MOSFET characteristics as controlled by the Gate-Source bias, Vgs, and the Gate-Drain bias, Vgd.

First, this applet demonstrates the facts that the inversion channel at the Source-end is controlled by Vgs, and at the Drain-end by Vgd.  For an n-channel MOSFET, the inversion channel is present at the Source-end of channel if Vgs > Vt, and is present at the Drain-end of channel if Vgd > Vt. Use the arrows next to these voltages in the applet and observe that the blue n-channel is controlled at either end of the channel by these two voltages, respectively.

n-MOSFET: (1) Triode If Vgs > Vt and Vgd > Vt, then the n-channel is continuous all the way from S to D. The S and D are connected by a conductor (or a resistor) of a given resistance. The drain current increases if the voltage drop between S and D increases. The channel resistance depends on how much charge is injected at the S-end, which in turn is controlled by Vgs. The Drain current Id depends on both Vgs and Vgd (or Vds), and thus we call thgis region of operation a Triode.  (2) Saturation If Vgs > Vt and Vgd < Vt, then n-channel is presen (or induced) at the S-end, but the channel is depleted at D-end. That is, the n-channel is pinchedoff at the Drain-end. What happens to all the electrons injected into channel from Source ? Think about it. [answer]. Once the drain-end of channel is pinched off, the current becomes no longer depends on the voltage drop between S and D (actually there is a small dependence of Id on Vds. Why ? What is this phenomenon called ? answer).  (3) Cutoff  If Vgs < Vt (and of course, Vgd < Vt), then the n-channel is not induced and no current flows.

p-MOSFET: For all cases, the inequality reverses between Vgs (and Vgd) and Vt.


3. The Output Characteristics of MOSFET

n-MOSFET:

(1) Triode

For Vgs > Vt and Vds < Vds(sat) = Vgs - Vt (or equivalently, Vgd > Vt), the channel is continuous all the way from S to D. Thus the n-channel acts like a conductor (or resistor) whose conductance is proportional to the amount of electrons injected from Source. The channel current (or drain current) is given by



(2) Saturation

(3) Circuit model parameters

Input resistance: The electrically insulating Gate oxide layer prevents any flow of current from Gate to Source. In a common source configuration with Gate as the input and Drain as the Output, the input resistance is infinity.

Output resistance: The small-signal circuit model for output resistance in the Common-source configuration is calculated as follows. The drain-source voltage Vds is biased so that the MOSFET is in saturation. The ac output voltage is a small variation of Vds around the dc-bias point. As the Vds varies, the drain current Id (or Ids, saturated) varies a little due to the channel length modeulation. The variation in Ids, its ratio with the output voltage is equal to the output resistance. The channel length modulation effect is expressed as

and the output resistance is

Where


Carrier flow in channel under saturation:

Channel length modulation: