SPICE Simulation or other CAD Tools   

1. Physical Design with L-Edit

MOSFETs are the fundamental devices used in a CMOS integrated circuit. In fact, most logic networks are constructed entirely of MOSFETs. Other electrical elements, such as resistors and capacitors, appear only as parasitics from the physical implementation.

The most important geometrical parameters in the MOSFET are the gate oxide thickness, tox; the channel length, L; and the channel width, W. The value of tox is set in the fabrication, so that the circuit designer has no control over its value. The channel length and width, on the other hand, are determined by the layout of the transistor, and are the primary design variables used in circuit design.

A physical design CAD software, such as L-EditTM, is used by circuit designers for the layout design. The layout design determines L and W, and thus some of the MOSFET device parameters. Interested students are encouraged to further find out about the CAD system L-EditTM by clicking this link. A good reference book on using this CAD system for the CMOS IC design is given below. The L-Edit's layout of R136 chip is here.

The geometric parameters, L and W, affect the device parameters such as gate capacitance and the transconductance.

(1) Capacitance

The basic capacitor formed by Gate(Metal or Polysilicon)-Oxide-Channel(inversion) is described by a capacitance per unit area:

where EPSILONox = (3.9)(8.854x10-14 Farads/cm) = 3.45x10-13 F/cm is the permitivity of silicon dioxide. For example, a 200 A thick gate oxide has Cox = 1.73 x 10-8 F/cm2 = 0.173 fF/um2. The total Gate capacitance is given by

Note that L' is the drawn channel length, which is a little greater than the actual channel length L.

(2) Transconductance

For non-saturated MOSFET (i.e., Triode region: Vgd > VTn or Vds < Vds(sat) = Vgs - VTn), the drain current is given by


Here un is the surface electron mobility in the channel. In a typical CMOS process, un ~= 550 - 600 cm2/Vs.

For a saturated MOSFET (i.e., Vgd < VTn or Vds > Vds(sat) ), the saturated drain current is given by

where LAMBDA is the channel length modulation factor. As the normal active region of operation is this saturated region, the value of LAMBDA gives the measure of dependence of the output current (Id) on the output voltage (Vds). The small signal circuit parameter, output resistance ro is related to LAMBDA by

In digital design, it is common to approximate LAMBDA = 0. Analog circuits, however, are often sensitive to LAMBDA or ro.

The threshold voltage Vt (VTn for nMOS and Vtp for pMOS) are affected by the bias applied between Source and the silicon bulk, VSB. For further discussion click here. The basic electrical parameters are set by the processing technology. Click here for further discussion.


John P. Uyemura, Physical Design of CMOS Integrated Circuits Using L_EDITTM, PWS Publishing, 1995. (ISBN 0-534-94326-8)

2. SPICE Simulation of the MOSFET Device:  the MOSFET I-V Characteristics

The presence of a MOSFET in a circuit is described in the SPICE input file using an element statement beginning with the letter M.    A (unique) name is appended to the M to identify each MOSFET in the circuit. This name is followed by a list of nodes to which the drain, gate, source, and substrate (body) of the MOSFET are connected.

MOSFET Circuit Symbol and SPICE Description

Element Symbol

SPICE Description

NMOS img Mname d g s sub MOS_name L=value W=value
.MODEL MOS-name NMOS (parameter=value ...)
PMOS img Mname d g s sub MOS_name L=value W=vaue
.MODEL MOS-name PMOS (parameter=value ...)

The following figure shows a SPICE curve-tracer arrangement for calulating the i-v characteristics of a MOSFET. The iD vs. VDS characteristic is obtained by sweeping VDS (say over 0 - 10 V) while keeping VGS constant; and the IDS vs. VGS is generated by sweeping VGS (e.g., over 0 - 10 V) while VDS is held constant at a value > VDS(sat).


The SPICE input file (or netlist) for computing iD vs. VDS is as follows. The MOSFET device parameters are assumed as: Vt = +2V, unCox = 20 uA/V2, LAMBDA=0 (or 0.05) V-1, L=10 um, and W=400 um. VGS is set at +3 V, and the VDS is swept over 0 - 10 V in 100-mV increments.

** Circuit Description **
* bias condition
Vds 1 0 DC +10V   ; this is arbitrary - we will sweep it
Vgs 2 0 DC +3V
M1 1 2 0 0 nmos_enhance L=10u W=400u
* model statement (Level 1 by default)
.MODEL nmos_enhance nmos (kp=20u Vto=+2 lambda=0)
** analysis request **
.DC Vds 0V 10V 100mV
** output requests **
.Plot DC I(Vds) V(1)

The result of this analysis is plotted below:


The iD vs. VDS with the channel length modulation parameter set at LAMBDA=0.05V-1 is also shown in the above figure. This curve is simulated using the same netlist except the .model statement:
.MODEL nmos_enhance nmos (kp=20u Vto=+2V lambda=0.05)

You can check the incremental drain-source resistance for LAMBDA=0.05 is about 49 kOhm. This is consistent with: VA = 1/LAMBDA = 20V, ro = VA/Ids = 20V/400uA = 50 kOhm.

The iDS vs. VGS may be simulated using the following netlist:

** Circuit Description **
* bias conditions
Vds 1 0 DC +5V
Vgs 2 0 DC +3V     ; arbitrary -- we will sweep it
M1 1 2 0 0 nmos_enhance nmos (kp=20u Vto=+2 lambda=0)
** analysis requests **
.DC Vgs 0V 10V 100mV
** Output requests **
.Plot DC I(Vgs) V(2)

The result of this simulation is shown below:


The same netlist, but with a different channel length modulation parameter: LAMBDA=0.05 V-1 is also shown.

G.W.Roberts and A.S.Sedra, SPICE, 2nd ed., Oxford Univ. Press, 1997 (ISBN 0-19-510842-6)