User can vary the threshold voltages, VTN and VTP, of NMOS and PMOS transistors relative to the voltage limits of the logic 0, VIL, and logic 1, VIH, at the input.  User can experiment with these settings and discover under what conditions of VT the Inverter operates correctly.

CMOS Inverter Operation : Introduction   alternative intro.

A CMOS gate, the building block of a digital IC, is composed of n-channel (NMOS) and p-channel (PMOS) metal-oxide-semiconductor field effect transistors (MOSFET's).  In the circuit diagram, PMOS devices appear in the upper portion (connected to the DC bias VCC) and NMOS devices appear in the lower portion (connected to the ground potential, GND).

For the operation of a CMOS gate, the input Vin, connected to the Gates of both NMOS and PMOS devices, turns ON one device type and turns OFF the other device type.  The ON/OFF behavior of a MOSFET device depends on whether the voltage difference between Gate and Source, Vgs, is greater or less than the threshold voltage, VT, which is the physical property that is intrinsic to the specific tansistor device1.  When a MOSFET device is ON, its channel region (the tall rectangle in the middle of the transistor symbol, the left-hand-side diagram) is filled with charge carriers (blue for electrons and red for holes) and thus that device electrically connects (or short circuits) the output, Vout, to the high voltage VCC or to low voltage GND.

For the CMOS inverter, Vout is at VCC (i.e., logic 1) if the PMOS is ON and the NMOS is OFF.  Vout is at GND (i.e., logic 0) if the PMOS is OFF and the NMOS is ON. Since the transistor ON/OFF behavior is controlled by the input voltage Vin, the output Vout is determined by the Inverter gate and the input Vin as Table 2 shows.  The CMOS inverter operation can be learned from the following applet program.  

You can hide the right-hand-side portion applet by clicking on the appropriate button, and use the left-hand-side to see the ON/OFF behavior of the MOSFET devices in response to the input Vin.  This determines the output, Vout.

  1. Left-hand side is the circuit diagram of CMOS Inverter circuit.  Right-hand side is the input voltage range for logic 1 (red region) and logic 0 (blue region), and the Threshold Voltage of PMOS (VTp) and NMOS (VTn) relative to the minimum V for logic 1 and maximum V for logic 0.
  2. When the threshold voltages are such that VIL < VTn < VIH and VIL < VCC + VTp < VIH, the Inverter circuit functions properly : Vout = 1 for Vin = 0, etc.  Here, VIL = maximum input voltage for logic 0,  VIH = minimum input voltage for logic 1.
  3. Therefore, for a given operating voltage for the logic 0 and 1, there is only a finite window for the Threshold voltage for the circuit to function properly.  This is so-called the threshold voltage matching issue.

Usage Instruction:
  • Mouse click on the region around Vin to change the digital input.  The output Vout responds.
  • Mouse drag the VTn or VTp, in the right-hand side figure, to change the threshold voltage wrt VIL and VIH.
    1. The circuit functions normally only when the threshold voltage of the MOSFET transistors is right : i.e., VIL < (VTn, VCC + VTp) < VIH.  
    2. The circuit does not function normally if the threshold voltages, VTn and VCC + VTp, lie outside the permitted range.
    3. Given the bias voltage VCC of the circuit, you can see what values of VTp and VTn are permitted.  The NMOS and PMOS devices should be designed to have their VT's fall within this range.  
    4. The control of MOSFET VT is done by controlling the doping level of the MOSFET channel region (under the Gate) using the ion implantation technology.

        Program by Ka Ho Cheung,
        Supervision Prof. C. R. Wie.
    (c) Copyright, 1997-1998, C.R.Wie and K.H.Cheung

    Notes :

    Table 1. Relationship between gate-source voltage, Vgs, and the threshold voltage, VT, for MOSFET Operations

    channel OFF channel ON
    PMOS Vgsp > VTp
    Vin > VTp + VCC
    Vgsp < VTp
    Vin < VTp + VCC
    NMOS Vgsn < VTn
    Vin < VTn
    Vgsn > VTn
    Vin > VTn

    Note:  The gate-source voltage, Vgs, is related to the input Vin as follows: Vgsp = Vin - VCC, and Vgsn = Vin.

    2. Table 2.  The output voltage and the corresponding input voltage for a normally operating CMOS inverter gate.




     0 (GND) 


    1 (VCC)