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*Mathematical Algorithm*

VI = Low (V1) to High (V2)

- V
_{I}= V_{2} - i
_{B}= I_{B2} - i
_{C}(t) = - 0 for t < t
_{d1}; - 0 for t
_{d1}< t < t_{d1}+ t_{d2}; - i
_{C}(t) for t_{d1}+ t_{d2 }< t < t_{d} - td = td1 + td2 + td3
- td1 = Emitter junction capacitance charges from that at V1 to that at 0.5V bias (cut-in bias)
- td1 = R
_{B}(C_{je}+C_{jc}) ln[(V_{2}-V_{1})/(V_{2}- 0.5)] - td2 = First minority carriers arrive at the Collector junction.
- td2 = (1/w
_{T})/3 = 2p/3f_{T}where, - f
_{T}= freq. at which CE current gain drops to unity. - td3 = iC increases from 0 to 0.1 Isat
- i
_{C}(t) = bI_{B2}[1 - exp(-t / t)]